Cadence Design Systems, Inc. announce that hotfix version 6 for 16.60 release available. A hot fix is a software maintenance package containing a small number of code fixes, designed to fix a small number of critical problems. A hot fix enables a customer to receive fixes for urgent problems, without having to wait for the next service pack.
Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.
This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industry’s first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
DATE: 05-22-2013 HOTFIX VERSION: 010
CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================================================================
1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6
1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border
1131775 ADW LRM LRM error with local libs & TDA
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor
Home Page : http://cadence.com
Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.
This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industry’s first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
DATE: 05-22-2013 HOTFIX VERSION: 010CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================================================================
1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6
1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border
1131775 ADW LRM LRM error with local libs & TDA
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.
1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering
1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor
Home Page : http://cadence.com
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